`include "timescale.v"
`include "uart_defines.v"

module uart_top	(
	clk, 
	rst,
	cs,
	wr,
	rd,
	read_addr,
	write_addr,
	data_in,
	data_out,
	int_o,

	// UART	signals
	// serial input/output
	stx_o,
	srx_i
	);

input 		 clk;

// SFR interface
input 		      rst;
input		      cs;
input		 	  wr;
input		      rd;
input		[7:0] read_addr;
input		[7:0] write_addr;
input		[7:0] data_in;
output		[7:0] data_out;
output			  int_o;

// UART	signals
input 					 srx_i;
output 					 stx_o;

// Registers
uart_regs	regs(
	.clk		(	clk 		),
	.rst		(	rst			),
	.read_addr	(	read_addr	),
	.write_addr ( 	write_addr	),
	.data_in	(	data_in		),
	.data_out	(	data_out	),
	.wr			(	wr			),
    .rd			(	rd			),
	.cs			(	cs			),
	.stx_o		(	stx_o		),
	.srx_i		(	srx_i		),
 
	.int_o		(	int_o		)
);

endmodule


